A CMOS analog switch has an N channel MOS transistor and a P channel MOS transistor connected in parallel; opposite-phase control signals are input to the gates of each of the transistors, and the conducting state (on) and non-conducting state (off) of the NMOS transistor and the PMOS transistor are switched by the control signals. No matter what the potentials of the input voltage and output voltage between ground and the power supply voltage, the conducting state and non-conducting state are maintained.
In general, an NMOS transistor is in a conducting state when the gate-source voltage exceeds a positive threshold voltage VthN, but at less than the threshold voltage VthN is in a non-conducting state. Hence when the power supply voltage VDD is applied to the gate, the NMOS transistor is in the conducting state when the source is at a voltage between 0 and (VDD−VthN), but is in the non-conducting state when the source is at a voltage between (VDD−VthN) and VDD. Conversely, a PMOS transistor is in a conducting state when the gate-source voltage exceeds a negative threshold voltage VthP (when the gate is lower by VthP than the source), but is in the non-conducting state when the gate-source voltage is less than the threshold voltage VthP. Hence on applying the ground voltage VSS to the gate, when the source is at a voltage between VthP and VDD, the device is in the conducting state, but when the source is at a voltage between 0 and VthP, the device is in the non-conducting state.
Hence if an NMOS transistor and a PMOS transistor are connected in parallel, and if the power supply voltage VDD is applied to the NMOS transistor gate and the ground voltage VSS is applied to the PMOS transistor gate, a conducting state is maintained at any voltage between 0 and VDD at the sources and drains of the two transistors.
Further, a back gate voltage is applied to the substrate region below the gate electrode, and in general the back gate voltage Vbg is 0 V in the case of an NMOS transistor and is the power supply voltage VDD in the case of a PMOS transistor.
Such a CMOS analog switch is described in Japanese Patent Application Laid-open No. H9-252241 and Japanese Patent Application Laid-open No. H10-41798.
However, the withstand voltage of the gate insulating film (hereafter called the “gate withstand voltage”) provided between the gate electrode and the substrate in a MOS transistor is comparatively low. If on the other hand the range 0 V to VDD of voltages applied at the input and output terminals of a CMOS analog switch is large, there are cases in which the voltage difference between the gate voltage Vg and the back gate voltage Vbg may exceed the gate withstand voltage. In such cases, the MOS transistor fails.
For this reason, it is necessary to hold the back gate voltage Vbg at a prescribed voltage and ensure that the voltage difference between the gate voltage Vg and the back gate voltage Vbg does not exceed the gate withstand voltage.
However, if the back gate voltage is made a voltage other than the ground voltage VSS or the power supply voltage VDD, the substrate region is forward-biased relative to the source/drain region connected to the input/output terminals of the CMOS analog switch, a leakage current occurs, and the input terminal voltage is no longer transmitted to the output terminal.